We are pleased to announce the first International Workshop on Performance, Portability and Productivity in HPC (P3HPC); an opportunity for researchers to share ideas, practical experiences, and methodologies for tackling the compelling problems that lie at the intersection of performance, portability and productivity.

We are particularly interested in research that addresses the complexities of real-life applications and/or realistic workloads, the composability challenges arising from the use of bespoke solutions, and the desire to “future-proof” applications in the long term.

Authors are invited to submit novel research from all areas concerned with performance, portability and productivity. The workshop is anticipated to attract a diverse and cross-disciplinary audience from industry and academia, bringing together: compiler, language and runtime experts; performance engineers; and domain scientists. Input from such a variety of experiences is critical to developing effective and productive solutions to performance portability, and tracking the highlights and lowlights of community experiences is key to identifying common themes and best practices.

Topics of interest include:

• Extensions to standard languages, libraries and runtimes such as C/C++, Fortran, OpenMP, OpenACC, OpenCL
• Algorithmic and application development techniques
• Software tools, libraries, domain specific languages and other abstractions
• Case studies documenting efforts to run across multiple diverse platforms using state-of-the-art tools and techniques
• Achieving performance portability for legacy codes
• Preparing applications for unexpected changes in architecture
• Definitions of and metrics for measuring performance portability
• Productivity concerns related to performance portability

Important Dates

• June 4: Submissions Open
• August 27 September 3rd: Submission Deadline
• September 17 September 24th: Author Notification
• October 8: Camera Ready Submissions
• November 16: Workshop Day (AM only)

Submission Guidelines

Authors are invited to submit original papers of no more than 10 pages, including tables, figures and your appendices, but not including references nor the reproducibility appendix. All submissions should be formatted according to the IEEE Conference Proceedings format.

Papers should be submitted electronically via the SC18 Linklings site.

Full papers will be published in the IEEE Xplore digital library in collaboration with IEEE TCHPC.

Reproducibility Initiative

The P3HPC workshop will follow a reproducibility initiative similar to SC technical papers: authors are encouraged to submit an appendix of no more than two pages detailing available artifacts and any steps taken to increase the trustworthiness of their results (see https://sc18.supercomputing.org/sc-reproducibility-initiative/).

The nature of performance portability involves demonstrated performance across multiple architectures, hence authors should describe artifact components across all architectures employed, such as compiler, runtime and application configurations. Authors should clearly document and explain the reasoning behind such configuration differences, to assist future researchers seeking to reproduce their experiments on future architectures.